1. Field of the Invention
The present invention relates to a field programmable gate array (FPGA) which is reconfigured in response to configuration data values which are transferred from a frame register to an array of configuration memory cells. More specifically, the present invention relates to a method and structure for enabling the partial reconfiguration of such an FPGA.
2. Discussion of Related Art
FIG. 1 is a schematic diagram of a portion of a conventional FPGA 100. FPGA 100 includes a frame register 110 which receives and stores a plurality of configuration data values. These configuration data values are typically received from an external source. The configuration data values are transferred from frame register 110 to an array of configuration memory cells, which includes configuration memory cells 151-156. The configuration data values stored in configuration memory cells 151-156 are provided to control predetermined programmable interconnection points (PIPs) and to define lookup table contents. The PIPs and lookup tables configure the FPGA in response to the configuration data values. Such a configuration structure is discussed by Freeman in U.S. Pat. No. Re 34,363 (See, particularly FIG. 5), which is hereby incorporated by reference in its entirety.
The configuration memory cells 151-156 are arranged in an array of rows and columns. Thus, configuration memory cells 151 and 152 are in a first row of the array, and configuration memory cells 151, 153 and 155 are in a first column of the array. The configuration data values are written from frame register 110 to the array on a column-by-column basis. For example, configuration data values are written to the first column of the array as follows. First, the configuration data values to be written to the first column are stored in frame register 110. A logic high write enable signal WE is then applied to the gates of row access transistors 111-113, thereby turning on these transistors. As a result, the configuration data values are routed from frame register 110, through write buffers 101-103 and row access transistors 111-113, to row lines 121-123. A logic high column select signal (CS1) is asserted on a column select line 131. This column select line 131 is coupled to cell access transistors 141, 143 and 145 (i.e., the cell access transistors associated with the first column of the array). The logic high CS1 signal turns on the cell access transistors 141, 143 and 145, thereby allowing the configuration data values to be written to the associated configuration memory cells 151, 153 and 155. Other configuration data values are written to the other columns of the array in the same manner until the FPGA is completely configured.
The asserted column select signal (CS1) has a full Vcc supply voltage of 5 Volts during a write operation. This high voltage ensures that the cell access transistors 141, 143 and 145 are sufficiently biased (i.e., turned on hard) to enable the configuration data values to be written to the associated configuration memory cells.
The configuration data values can also be read from the configuration memory cells to frame register 110. Like the write operations, the read operations are performed on a column-by-column basis. However, read operations are slightly more complicated than write operations because each of the row lines 121, 122 and 123 has an associated parasitic capacitance 121C, 122C and 123C. Because the row lines 121-123 are relatively long, these capacitances 121C-123C are large enough to store charges which are capable of changing the state of the configuration memory cells during a read operation if the associated cell access transistors are fully turned on.
Accordingly, during a read operation, all of the row lines 121-123 are pre-charged to a logic high voltage level. Next, the cell access transistors are biased with a reduced voltage column select signal. The cell access transistors are biased with a reduced voltage for the following reason. If the cell access transistors were biased with a full Vcc supply voltage of 5 Volts, then the effective impedance of the cell access transistors would be relatively small. As a result, the charges stored by the row line capacitances could be sufficient to flip the states of those configuration memory cells storing logical 0's.
In one example, after the row line capacitances 121C-123C are pre-charged to the Vcc supply voltage (i.e., 5 Volts), the column select signal CS1 is asserted at a reduced voltage of 2.5 Volts. The reduced voltage column select signal CS1 causes cell access transistors 141, 143 and 145 to turn on weakly. At this time, cell access transistors 141, 143 and 145 exhibit relatively high impedances. Under these conditions, those configuration memory cells which store logic low data values cause the associated row lines to discharge. For example, if configuration memory cell 151 stores a logic low data value, then the pre-charged row line capacitance 121C is discharged through the weakly turned on cell access transistor 141. As a result, the status of configuration memory cell 151 is not disturbed during the read operation.
The pre-charged row lines also help to maintain the status of configuration memory cells which store logic high data values. For example, if configuration memory cell 153 stores a logic high data value, then the pre-charged status of row line 122 prevents the row line capacitance 122C from pulling down configuration memory cell 153 when the column select signal CS1 is asserted. As a result, the status of configuration memory cell 153 is not disturbed during the read operation.
As previously discussed, all write operations and all read operations must be performed on a column-by-column basis. The previously described operating parameters prohibit the partial reconfiguration of a column. That is, it is not possible to write configuration data values to fewer than all of the configuration memory cells in a column. As a result, the reconfiguration of conventional FPGAs is undesirably limited.
It would therefore be desirable to have an FPGA with partially reconfigurable columns of configuration memory cells. That is, it is desirable to have an FPGA in which selected configuration memory cells within a column of configuration memory cells can be reconfigured.